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19-2551; Rev 0; 6/02
Low-Power, 16-Bit Analog-to-Digital Converters with Parallel Interface
General Description
The MAX1165/MAX1166 16-bit, low-power, successiveapproximation analog-to-digital converters (ADCs) feature automatic power-down, factory-trimmed internal clock, and a 16-bit wide (MAX1165) or byte wide (MAX1166) parallel interface. The devices operate from a single +4.75V to +5.25V analog supply and a +2.7V to +5.25V digital supply. The MAX1165/MAX1166 use an internal 4.096V reference or an external reference. The MAX1165/MAX1166 consume only 1.8mA at a sampling rate of 165ksps with external reference and 2.7mA with internal reference. AutoShutdownTM reduces supply current to 0.1mA at 10ksps. The MAX1165/MAX1166 are ideal for high-performance, battery-powered, data-acquisition applications. Excellent dynamic performance and low power consumption in a small package make the MAX1165/ MAX1166 ideal for circuits with demanding power consumption and space requirements. The 16-bit wide MAX1165 is available in a 28-pin TSSOP package and the byte wide MAX1166 is available in a 20-pin TSSOP package. Both devices are available in either the 0C to +70C commercial, or the -40C to +85C extended temperature range.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Features
o 16-Bit Wide (MAX1165) and Byte Wide (MAX1166) Parallel Interface o High Speed: 165ksps Sample Rate o Accurate: 2LSB INL, 16 Bit No Missing Codes o 4.096V, 35ppm/C Internal Reference o External Reference Range: +3.8V to +5.25V o Single +4.75V to +5.25V Analog Supply Voltage o +2.7V to +5.25V Digital Supply Voltage o Low Supply Current 1.8mA (External Reference) 2.7mA (Internal Reference) 0.1A (10ksps, External Reference) o Small Footprint 28-Pin TSSOP Package (16-Bit Wide) 20-Pin TSSOP Package (Byte Wide)
MAX1165/MAX1166
Ordering Information
PART MAX1165ACUI* MAX1165BCUI MAX1165CCUI MAX1165AEUI* MAX1165BEUI* MAX1165CEUI* TEMP RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 TSSOP 28 TSSOP 28 TSSOP 28 TSSOP 28 TSSOP 28 TSSOP INL 2 2 4 2 2 4
Applications
Temperature Sensor/Monitor Industrial Process Control I/O Boards Data-Acquisition Systems Cable/Harness Tester Accelerometer Measurements Digital Signal Processing
*Future product--contact factory for availability. Ordering Information continued at end of data sheet.
Typical Operating Circuit
+5V ANALOG +5V DIGITAL
0.1F
0.1F P DATA BUS
Pin Configurations appear at end of data sheet. Functional Diagram appears at end of data sheet.
ANALOG INPUT
AIN
AVDD
DVDD D0-D15
MAX1165
R/C CS RESET
EOC REF REFADJ
AGND DGND
0.1F
4.7F
________________________________________________________________ Maxim Integrated Products
1
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND ........................................-0.3V to (AVDD + 0.3V) AGND to DGND.....................................................-0.3V to +0.3V AIN, REF, REFADJ to AGND....................-0.3V to (AVDD + 0.3V) CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V Digital Output (D15-D0, EOC) to DGND ..............................................-0.3V to (DVDD + 0.3V) Maximum Continuous Current Into Any Pin ........................50mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 10.9mW/C above+70C) ........879mW 28-Pin TSSOP (derate 12.8mW/C above +70C) .....1026mW Operating Temperature Ranges MAX116_ _CU_ ...................................................0C to +70C MAX116_ _EU_ ................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7F, CREFADJ = 0.1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution Relative Accuracy (Note 1) N MAX116_A INL MAX116_B MAX116_C Differential Nonlinearity DNL No missing codes over temperature MAX116_C Transition Noise Offset Error Gain Error Offset Drift Gain Drift DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 1kHz, VIN = 4.096VP-P, 165ksps) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Sample Rate Aperture Delay Aperture Jitter ANALOG INPUT Input Range Input Capacitance VAIN CAIN 0 40 VREF V pF fSAMPLE 27 <100 165 ksps ns ps SINAD SNR THD SFDR -3dB point SINAD > 81dB 92 86 87 90 90 -102 105 4 33 -90 dB dB dB dB MHz kHz (Note 2) RMS noise, external reference, includes quantization noise Internal reference 0.65 0.7 0.05 0.002 0.6 0.2 1 0.02 MAX116_A MAX116_B -1 16 2 2 4 1 1.5 2 LSBRMS LSBRMS mV %FSR ppm/C ppm/C LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7F, CREFADJ = 0.1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INTERNAL REFERENCE REF Output Voltage REF Output Tempco REF Short-Circuit Current Capacitive Bypass at REFADJ Capacitive Bypass at REF REFADJ Input Leakage Current EXTERNAL REFERENCE REFADJ Buffer Disable Threshold REF Input Voltage Range REF Input Current DIGITAL INPUTS/OUTPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Supply AVDD DVDD 165ksps Internal reference Analog Supply Current IAVDD External reference 100ksps 10ksps 1ksps 165ksps 100ksps 10ksps 1ksps 4.75 2.7 2.7 2.0 1.0 1.0 1.8 1.1 0.1 0.01 2.3 mA 5.25 AVDD 3.2 V V VIH VIL IIN VHYST CIN VOH VOL IOZ COZ ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V ISINK = 1.6mA, DVDD = +2.7V to +5.25V, AVDD = +5.25V D0-D15 0.1 15 DVDD 0.4 0.4 10 VIH = 0 or DVDD 0.1 0.1 15 0.7 x DVDD 0.3 x DVDD 1 V V A V pF V V A pF IREF To power down the internal reference Internal reference disabled VREF = +4.096V, fSAMPLE = 165ksps Shutdown mode AVDD 0.4 3.8 50 0.1 AVDD 0.1 AVDD 120 V V A VREF TCREF IREFSC CREFADJ CREF IREFADJ 0.1 1 20 4.056 4.096 25 10 4.136 V ppm/C mA F F A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1165/MAX1166
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7F, CREFADJ = 0.1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS 165ksps Digital Supply Current IDVDD D0-D15 = all zeros 100ksps 10ksps 1ksps Full power-down Shutdown Supply Current ISHDN REF and REF buffer enabled (standby mode) IAVDD IDVDD IAVDD IDVDD (Note 3) MIN TYP 0.5 0.3 0.03 0.003 0.5 0.5 1.0 0.5 68 5 5 1.2 5 A mA A dB MAX 0.7 mA UNITS
Power-Supply Rejection Ratio
PSRR
AVDD = +5V 5%, full-scale input (Note 4)
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 4.7F, CREFADJ = 0.1F, CLOAD = 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25C.)
PARAMETER Acquisition Time Conversion Time CS Pulse Width High CS Pulse Width Low (Note 5) R/C to CS Fall Setup Time R/C to CS Fall Hold Time CS to Output Data Valid HBEN Transition to Output Data Valid (MAX1166 Only) EOC Fall to CS Fall CS Rise to EOC Rise Bus Relinquish Time (Note 5) SYMBOL tACQ tCONV tCSH tCSL tDS tDH tDO tDO1 tDV tEOC tBR VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 5.25V VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 5.25V VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 5.25V VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 5.25V VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 5.25V 0 40 80 40 80 (Note 5) VDVDD = 4.75V to 5.25V VDVDD = 2.7V to 5.25V 40 40 60 0 40 60 40 80 40 80 CONDITIONS MIN 1.1 4.7 TYP MAX UNITS s ns ns ns ns ns ns ns ns ns
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 2: Offset nulled. Note 3: Shutdown supply currents are typically 0.5A, maximum specification is limited by automated test equipment. Note 4: Defined as the change in positive full scale caused by a 5% variation in the nominal supply. Note 5: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
4
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface
Typical Operating Characteristics
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7F, CREFADJ = 0.1F, TA = +25C, unless otherwise noted.)
INL vs. OUTPUT CODE
MAX1165/66 toc01
MAX1165/MAX1166
DNL vs. OUTPUT CODE
MAX1165/66 toc02
IAVDD + IDVDD SUPPLY CURRENT vs. SAMPLE RATE
MAX1165/66 toc03
2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 16384 32768 OUTPUT CODE 49152
2.0 1.5 1.0 DNL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0
10
1 SUPPLY CURRENT (mA)
0.1
0.01
0.001
0.0001 0 16384 32768 OUTPUT CODE 49152 66536 0.01 0.1 1 10 100 1000 SAMPLE RATE (ksps)
65536
IAVDD + IDVDD SUPPLY CURRENT vs. TEMPERATURE
MAX1165/66 toc04
IAVDD + IDVDD SHUTDOWN CURRENT vs. TEMPERATURE
4.5 SHUTDOWN CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0
MAX1165/66 toc05
INTERNAL REFERENCE vs. TEMPERATURE
4.126 INTERNAL REFERENCE (V) 4.116 4.106 4.096 4.086 4.076 4.066 4.056
MAX1165/66 toc06
3.5 3.0 SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 SAMPLE RATE = 165ksps 0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
5.0
4.136
0.5 0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-40
-20
0
20
40
60
80
TEMPERATURE (C)
OFFSET ERROR vs. TEMPERATURE
MAX1165/66 toc07
GAIN ERROR vs. TEMPERATURE
MAX1165/66 toc08
SINAD vs. FREQUENCY
90 80 70 SINAD (dB) 60 50 40 30 20 10 0 SAMPLE RATE = 165ksps 0.1 1 10 100
MAX1165/66 toc09
1000 800 600 OFFSET ERROR (V) 400 200 0 -200 -400 -600 -800 -1000 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0.020 0.015 GAIN ERROR (%FSR) 0.010 0.005 0 -0.005 -0.010 -0.015 -0.020 -40 -20 0 20 40 60 80 TEMPERATURE (C)
100
FREQUENCY (kHz)
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7F, CREFADJ = 0.1F, TA = +25C, unless otherwise noted.)
THD vs. FREQUENCY
MAX1165/66 toc10
SFDR vs. FREQUENCY
MAX1165/66 toc11
0 -10 -20 -30 -50 -60 -70 -80 -90 -100 -110 -40
SAMPLE RATE = 165ksps
120 110 100 90 80 70 60 50 40 30 20 10 0
SFDR (dB)
THD (dB)
SAMPLE RATE = 165ksps 0.1 1 10 100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FFT AT 1kHz
SAMPLE RATE = 165ksps -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 0 20 40 FREQUENCY (kHz) 60 80 SNR (dB)
MAX1165/66 toc12
SNR vs. FREQUENCY
120 110 100 90 80 70 60 50 40 30 20 10 0
MAX1165/66 toc13
0
SAMPLE RATE = 165ksps 0.1 1 10 100
FREQUENCY (kHz)
6
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface
Pin Description
PIN 1 2 3 4 5 6 7 8 1 2 3 4 -- -- -- -- D8 D9 D10 D11 D12 D13 D14 D15 NAME D4/D12 D5/D13 D6/D14 D7/D15 -- -- -- -- Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output. D15 is the MSB. Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output (MSB) Read/Convert Input. Power up and put the MAX1165/MAX1166 in acquisition mode by holding R/C low during the first falling edge of CS. During the second falling edge of CS, the level on R/C determines whether the reference and reference buffer power down or remain on after conversion. Set R/C high during the second falling edge of CS to power down the reference and buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third falling edge of CS to put valid data on the bus. End of Conversion. EOC drives low when conversion is complete. Analog Supply Input. Bypass with a 0.1F capacitor to AGND. Analog Ground. Primary analog ground (star ground). Analog Input Analog Ground. Connect pin 14 to pin 12 (MAX1165). Connect pin 10 to pin 8 (MAX1166). Reference Buffer Output. Bypass REFADJ with a 0.1F capacitor to AGND for internal reference mode. Connect REFADJ to AVDD to select external reference mode. Reference Input/Output. Bypass REF with a 4.7F capacitor to AGND for internal reference mode. External reference input when in external reference mode. Reset Input. Logic high resets the device. High-Byte Enable Input. Used to multiplex the 14-bit conversion result: 1: Most significant byte available on the data bus. 0: Least significant byte available on the data bus. Convert Start. The first falling edge of CS powers up the device and enables acquire mode when R/C is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result onto the bus when R/C is high. Digital Ground Digital Supply Voltage. Bypass with a 0.1F capacitor to DGND. Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output Three-State Digital Data Output MAX1165 MAX1166 MAX1165 MAX1166 FUNCTION
MAX1165/MAX1166
9
5
R/C
10 11 12 13 14 15 16 17 --
6 7 8 9 10 11 12 -- 13
EOC AVDD AGND AIN AGND REFADJ REF RESET HBEN
18 19 20 21 22 23 24 25 26 27 28
14 15 16 17 18 19 20 -- -- -- -- D0 D1 D2 D3 D4 D5 D6 D7
CS DGND DVDD D0/D8 D1/D9 D2/D10 D3/D11 -- -- -- --
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
DVDD 1mA D0-D15 CLOAD = 20pF 1mA DGND a) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z CLOAD = 20pF DGND D0-D15
Analog Input
The equivalent input circuit is shown in Figure 4. A switched capacitor digital-to-analog converter (DAC) provides an inherent T/H function. The single-ended input is connected between AIN and AGND.
Input Bandwidth
The ADC's input-tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, use anti-alias filtering.
b) HIGH-Z TO VOL, VOH TO VOL, AND VOL TO HIGH-Z
Figure 1. Load Circuits
Detailed Description
Converter Operation
The MAX1165/MAX1166 use a successive-approximation (SAR) conversion technique with an inherent trackand-hold (T/H) stage to convert an analog input into a 16-bit digital output. Parallel outputs provide a highspeed interface to most microprocessors (Ps). The Functional Diagram shows a simplified internal architecture of the MAX1165/MAX1166. Figure 3 shows a typical application circuit for the MAX1166.
tCSH
Analog Input Protection
Internal protection diodes, which clamp the analog input to AVDD and/or AGND, allow the input to swing from AGND - 0.3V to AVDD + 0.3V, without damaging the device. If the analog input exceeds 300mV beyond the supplies, limit the input current to 10mA.
tCSL
CS tACQ REF POWERDOWN BIT tDH EOC tCONV HIGH-Z D0-D15 tDO DATA VALID tBR HIGH-Z tDS tDV tEOC
R/C
HBEN* tDO1 D8/D15- D0/D7* *HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1166 ONLY. HIGH-/LOWBYTE VALID tBR HIGH-/LOWBYTE VALID
Figure 2. MAX1165/MAX1166 Timing Diagram 8 _______________________________________________________________________________________
Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
+5V ANALOG +5V DIGITAL
REF TRACK CAPACITIVE DAC ZERO CSWITCH 3pF HOLD AGND CDAC = 32pF RIN 800 TRACK
0.1F
0.1F
AIN
AVDD ANALOG INPUT AIN
DVDD D0-D7 OR D8-D15
P DATA BUS
HOLD
MAX1166
EOC R/C CS HIGH BYTE LOW BYTE HBEN REF REFADJ AGND DGND 0.1F 4.7F
AUTOZERO RAIL
Figure 4. Equivalent Input Circuit
Power-Down Modes
Select standby mode or shutdown mode with the R/C bit during the second falling edge of CS (see the Selecting Standby or Shutdown Mode section). The MAX1165/MAX1166 automatically enter either standby mode (reference and buffer on) or shutdown (reference and buffer off) after each conversion depending on the status of R/C during the second falling edge of CS.
Figure 3. Typical Application Circuit for the MAX1166
Track and Hold (T/H)
In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open and the capacitive DAC samples the analog input. During the acquisition, the analog input (AIN) charges capacitor CDAC. The acquisition ends on the second falling edge of CS. At this instant, the T/H switches open. The retained charge on CDAC represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion time to restore node ZERO to zero within the limits of 16-bit resolution. Force CS low to put valid data on the bus at the end of the conversion. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal. Use the following formula to calculate acquisition time: tACQ = 11 (RS + RIN) 35pF where R IN = 800, R S = the input signal's source impedance, and t ACQ is never less than 1.1s. A source impedance less than 1k does not significantly affect the ADC's performance. To improve the input signal bandwidth under AC conditions, drive AIN with a wideband buffer (>4MHz) that can drive the ADC's input capacitance and settle quickly.
Internal Clock
The MAX1165/MAX1166 generate an internal conversion clock. This frees the microprocessor from the burden of running the SAR conversion clock. Total conversion time after entering hold mode (second falling edge of CS) to end of conversion (EOC) falling is 4.7s (max).
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the MAX1165/MAX1166 (Figure 2). The first falling edge of CS powers up the device and puts it in acquire mode if R/C is low. The convert start is ignored if R/C is high. The MAX1165/MAX1166 need at least 10ms (CREFADJ = 0.1F, CREF = 4.7F) for the internal reference to wake up and settle before starting the conversion if powering up from shutdown. The ADC can wake up, from shutdown, to an unknown state. Put the ADC in a known state by completing one "dummy" conversion. The MAX1165/MAX1166 are in a known state, ready for actual data acquisition, after the completion of the dummy conversion. A dummy conversion consists of one full conversion cycle. The MAX1165 provides an alternative reset function to reset the device (see the RESET section).
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
ACQUISITION CONVERSION DATA OUT ACQUISITION CONVERSION DATA OUT
CS
REF POWERDOWN BIT
CS
REF POWERDOWN BIT
R/C
R/C
EOC REF AND BUFFER
EOC REF AND BUFFER
Figure 5. Selecting Standby Mode
Figure 6. Selecting Shutdown Mode
Selecting Standby or Shutdown Mode
The MAX1165/MAX1166 have a selectable standby or low-power shutdown mode. In standby mode, the ADC's internal reference and reference buffer do not power down between conversions, eliminating the need to wait for the reference to power up before performing the next conversion. Shutdown mode powers down the reference and reference buffer after completing a conversion. The reference and reference buffer require a minimum of 10ms (CREFADJ = 0.1F, CREF = 4.7F) to power up and settle from shutdown. The state of R/C at the second falling edge of CS selects which power-down mode the MAX1165/ MAX1166 enter upon conversion completion. Holding R/C low causes the MAX1165/MAX1166 to enter standby mode. The reference and buffer are left on after the conversion completes. R/C high causes the MAX1165/ MAX1166 to enter shutdown mode and shut down the reference and buffer after conversion (Figures 5 and 6). When using an external reference, set the REF powerdown bit high for lowest current operation.
causes the reference and buffer to wake up and enter acquisition mode. To achieve 16-bit accuracy, allow 10ms (CREFADJ = 0.1F, CREF = 4.7F) for the internal reference to wake up.
Internal and External Reference
Internal Reference The internal reference of the MAX1165/MAX1166 is internally buffered to provide +4.096V output at REF. Bypass REF to AGND and REFADJ to AGND with 4.7F and 0.1F, respectively. Fine adjustments can be made to the internal reference voltage by sinking or sourcing current at REFADJ. The input impedance of REFADJ is nominally 5k. The internal reference voltage is adjustable to 1.5% with the circuit of Figure 7.
+5V 68k 100k 0.1F 150k
MAX1165 MAX1166
REFADJ
Standby Mode
While in standby mode, the supply current is reduced to less than 1mA (typ). The next falling edge of CS with R/C low causes the MAX1165/MAX1166 to exit standby mode and begin acquisition. The reference and reference buffer remain active to allow quick turn-on time. Standby mode allows significant power savings while running at the maximum sample rate.
Figure 7. MAX1165/MAX1166 Reference Adjust Circuit
Shutdown Mode
In shutdown mode, the reference and reference buffer are shut down between conversions. Shutdown mode reduces supply current to 0.5A (typ) immediately after the conversion. The falling edge of CS with R/C low
10
External Reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the MAX1165/ MAX1166s' internal buffer amplifier. When connecting an
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface
external reference to REFADJ, the input impedance is typically 5k. Using the buffered REFADJ input makes buffering the external reference unnecessary; however, the internal buffer output must be bypassed at REF with a 1F capacitor. Connect REFADJ to AVDD to disable the internal buffer. Directly drive REF using an external reference. During conversion the external reference must be able to drive 100A of DC load current and have an output impedance of 10 or less. REFADJ's impedance is typically 5k. The DC input impedance of REF is a minimum 40k. For optimal performance, buffer the reference through an op amp and bypass REF with a 1F capacitor. Consider the MAX1165/MAX1166s' equivalent input noise (38VRMS) when choosing a reference.
MAX1165/MAX1166
OUTPUT CODE FULL-SCALE TRANSITION 11...111 11...110 11...101
FS = VREF 1LSB = VREF 65536
00...011 00...010 00...001 00...000 0 1 2 3
FS
INPUT VOLTAGE (LSB) FS - 3/2LSB
Figure 8. MAX1165/MAX1166 Transfer Function
Reading a Conversion Result
EOC is provided to flag the microprocessor when a conversion is complete. The falling edge of EOC signals that the data is valid and ready to be output to the bus. D0-D15 are the parallel outputs of the MAX1165/ MAX1166. These three-state outputs allow for direct connection to a microcontroller I/O bus. The outputs remain high-impedance during acquisition and conversion. Data is loaded onto the bus with the third falling edge of CS with R/C high after tDO. Bringing CS high forces the output bus back to high impedance. The MAX1165/MAX1166 then wait for the next falling edge of CS to start the next conversion cycle (Figure 2). The MAX1165 loads the conversion result onto a 16-bit wide data bus while the MAX1166 has a byte-wide output format. HBEN toggles the output between the most/least significant byte. The least significant byte is loaded onto the output bus when HBEN is low and the most significant byte is on the bus when HBEN is high (Figure 2).
plexed, the input channel should be switched immediately after acquisition, rather than near the end of or after a conversion. This allows more time for the input buffer amplifier to respond to a large step change in input signal. The input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. At the beginning of acquisition, the internal sampling capacitor array connects to AIN (the amplifier output), causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the internal sampling capacitor with very little ripple. However, for AC use, AIN must be driven by a wideband buffer (at least 10MHz), which must be stable with the ADC's capacitive load (in parallel with any AIN bypass capacitor used) and also settle quickly. An example of this circuit using the MAX4434 is given in Figure 9.
RESET
Toggle RESET with CS high. The next falling edge of CS begins acquisition. This reset is an alternative to the dummy conversion explained in the Starting a Conversion section.
MAX1165 MAX1166
AIN ANALOG INPUT 40pF
10
Transfer Function
Figure 8 shows the MAX1165/MAX1166 output transfer function. The output is coded in standard binary.
MAX4434
Input Buffer
Most applications require an input buffer amplifier to achieve 16-bit accuracy. If the input signal is multiFigure 9. MAX1165/MAX1166 Fast Settling Input Buffer
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital ground planes with only one point connecting the two ground systems (analog and digital) as close to the device as possible. Route digital signals far away from sensitive analog and reference inputs. If digital lines must cross analog lines, do so at right angles to minimize coupling digital noise onto the analog lines. If the analog and digital sections share the same supply, then isolate the digital and analog supply by connecting them with a low-value (10) resistor or ferrite bead. The ADC is sensitive to high-frequency noise on the AV DD supply. Bypass AV DD to AGND with a 0.1F capacitor in parallel with a 1F to 10F low-ESR capacitor with the smallest capacitor closest to the device. Keep capacitor leads short to minimize stray inductance. noise error only and results directly from the ADC's resolution (N bits): SNR = (6.02 N + 1.76)dB where N = 16 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals: SignalRMS SINAD (dB) = 20 x log (Noise + Distortion)RMS
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1165/MAX1166 are measured using the end-point method.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = SINAD - 1.76 6.02
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of 1 LSB guarantees no missing codes and a monotonic transfer function.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + V5 THD = 20 x log V1 where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the time between samples. Aperture delay is the time between the rising edge of the sampling clock and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest frequency component.
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface
Functional Diagram
REFADJ HBEN* AVDD AGND DVDD DGND
MAX1165/MAX1166
5k REFERENCE
OUTPUT REGISTERS REF
16 OR 8*
16 OR 8*
D0-D15 OR D0/D7-D8/D15*
AIN CAPACITIVE DAC AGND
MAX1165 MAX1166
RESET** CLOCK CS R/C * BYTE WIDE (MAX1166 ONLY) **16-BIT WIDE (MAX1165 ONLY)
SUCCESSIVEAPPROXIMATION REGISTER AND CONTROL LOGIC
EOC
Ordering Information (continued)
PART MAX1166ACUP* MAX1166BCUP MAX1166CCUP MAX1166AEUP* MAX1166BEUP* MAX1166CEUP* TEMP RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP INL 2 2 4 2 2 4
Chip Information
TRANSISTOR COUNT: 15,140 PROCESS: BiCMOS
*Future product--contact factory for availability.
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface MAX1165/MAX1166
Pin Configurations
TOP VIEW
D8 1 D9 2 D10 3 D11 4 D12 5 D13 6 D14 7 D15 8 R/C 9 EOC 10 AVDD 11 AGND 12 AIN 13 AGND 14 28 D7 27 D6 26 D5 25 D4 24 D3 D4/D12 1 D5/D13 2 D6/D14 3 D7/D15 4 R/C 5 EOC 6 AVDD 7 AGND 8 AIN 9 AGND 10 20 D3/D11 19 D2/D10 18 D1/D9 17 D0/D8
MAX1166
16 DVDD 15 DGND 14 CS 13 HBEN 12 REF 11 REFADJ
MAX1165
23 D2 22 D1 21 D0 20 DVDD 19 DGND 18 CS 17 RESET 16 REF 15 REFADJ
TSSOP
TSSOP
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Low-Power, 16-Bit Analog-to-Digital Converter with Parallel Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP.EPS
MAX1165/MAX1166
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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